1. Field of the Invention
The present invention relates to a complementary current source circuit used in a Digital-to-Analog converter (hereinafter referred to as "D/A converter"), and more particularly to circuit means to provide a D/A converter's output with little overshoot.
2. Description of the Background Art
A D/A converter for converting a digital signal to an analog signal is an essential electronic device in the art of electronic apparatus for public welfare, such as apparatus for measurement, control, communication and image. For example, a circuit configuration of the D/A converter is shown in the following documents: (1) Naoki Kumazawa et al., "An 8 bit 150 MHz CMOS D/A converter with 2 Vp-p wide range output," Symposium on VLSI Circuits Digest of Technical Papers, pp. 55-56, June, 1990 and (2) Jean Michel Fournier and Patrice Senn, "A 130 MHz 8-b CMOS Video DAC for HDTV Applications," IEEE Journal of Solid-State Circuits, Vol. 26, No. 7, July, 1991. As is seen from these documents, the D/A converter comprises a plurality of complementary current source circuits, the number of which is determined as a function of the number of bits of the input signal (e.g., 2.sup.N complementary current source circuits are provided when the input signal of N bits is processed), and operates some of the complementary current source circuits in response to the input signal. When currents from the operating complementary current source circuits are collected and then flow into a resistance element of desired resistance value, an analog voltage in accordance with a digital signal can be obtained. Therefore, the complementary current source circuit is a key device in the D/A converter.
The circuit configuration of a complementary current source circuit used in a D/A converter in the prior art will be discussed, referring to its model. FIG. 14 is a circuit diagram of a complementary current source circuit having a main current source which consists of PMOS transistors, as shown in the above documents (1) and (2), while FIG. 15 is a circuit diagram of a complementary current source circuit having a main current source which consists of NMOS transistors. The complementary current source circuit discussed herein essentially consists of a main current source and driving circuits for driving switching transistors of the main current source. A CMOS inverter circuit as shown in these figures is the simplest driving circuit.
The complementary current source circuit of FIG. 14 essentially consists of a main source current 1 and driving circuits 2 and the complementary current source circuit of FIG. 15 essentially consists of a main current source 3 and driving circuits 4. In the discussion below, the reference characters and numerals represent the elements of FIG. 14 and those inside parentheses represent the elements of FIG. 15. The values of input signals S and S are generated and then applied to the gates of respective transistors in the driving circuits 2 (4). Transistors Q1 (Q8) and Q2 (Q9) in the main current source 1 (3) are switching transistors which have source terminals connected in common (hereinafter referred to as "common source"). The common source is connected to a transistor Q3 (Q10) for constant current source. A bias voltage is applied to the gate terminal of the transistor Q3 (Q10) so that the transistor Q3 (Q10) may always operate in a saturation region to pass a constant drain current. Complementary driving signals VG and VG are applied to the gate terminals of the transistors Q1 (Q8) and Q2 (Q9), respectively, through the driving circuits 2 (4) to alternately turn on and turn off the transistors Q1 (Q8) and Q2 (Q9). Thus, in response to the driving signal VG or VG, a switching is done by passing the drain current of the transistor Q3 (Q10) to an output terminal I.sub.out or I.sub.out. These figures also show resistance loads RL provided outside the D/A converter and floating capacitances Cx and Co which exist at an internal node and an external node, respectively. For example, in the D/A converter provided with 2.sup.N complementary current source circuits, an analog voltage V.sub.out in accordance with a digital signal can be obtained by collecting the currents from the complementary current source circuit which operates in response to the input signals S and S and applying the collected current to the resistance element RL of desired resistance value.
Having such a configuration as above, the complementary current source circuits used in the prior-art D/A converter has a problem as discussed below.
Referring to charts of FIGS. 16A to 16C showing a relation between input signals and output signals, an operation of the prior-art complementary current source circuit of PMOS configuration of FIG. 14 will be discussed. When the input signals S and S shown in FIG. 16A are inputted to the driving circuits 2, the driving signals VG and VG shown in FIG. 16B are generated. A voltage V.sub.X at the internal node X in the main current source once slightly fluctuates from a stationary value V.sub.X0 in a positive direction at a switching time and then converges on a voltage V.sub.X0 again, as shown in FIG. 16B. With this fluctuation of the voltage V.sub.X at the internal node X, the floating capacitance Cx at the internal node X once becomes charged and then discharged. In consequence, a surplus current is generated to thereby increase the output current (e.g., I.sub.out) and the output voltage (e.g., V.sub.out) developed across the resistance load RL fluctuates at a large slew rate, leading to an overshoot as shown in FIG. 16C. Therefore, it is disadvantageously impossible to achieve a short settling time.
Referring to charts of FIGS. 17A to 17C showing a relation between input signals and output signals, an operation of the prior-art complementary current source circuit of NMOS configuration of FIG. 15 will be discussed. In this case, a voltage V.sub.X at the internal node X in the main current source once slightly fluctuates from the stationary value V.sub.X0 in a negative direction at a switching time and then converges on a voltage V.sub.X0 again, as shown in FIG. 17B. With this fluctuation of the voltage V.sub.X at the internal node X, the floating capacitance Cx at the internal node once becomes charged and then discharged. In consequence, a surplus current is generated and the output voltage fluctuates at a large slew rate, leading to an overshoot as shown in FIG. 17C. Therefore, it is disadvantageously impossible to achieve a short settling time.
Since the switching transistors Q1 (Q8) and Q2 (Q9) in the complementary current source circuits of FIGS. 14 and 15 are simultaneously turned on or turned off, in particular, there arises a large fluctuation of the voltage V.sub.X at the internal node X and a great overshoot.
The settling time mentioned above refers to a time period until a stable analog signal is obtained in the D/A converter. A long settling time in the D/A converter leads to a delay of a processing for D/A conversion and accordingly it becomes impossible to keep up with an increasing advancement of the technique for speeding up the processing.